1. Technical Field of the Invention
This disclosure relates to a power supply circuit of a mobile phone, and more particularly to a power supply circuit including a power switching circuit that switches between the electric power supplied from a battery installed in a mobile phone and the electric power supplied from an AC adapter.
2. Description of the Related Art
In normal use of a mobile device, electric power is supplied to an electronic circuit from a battery installed inside the mobile device. In an environment where commercial electricity is available, an AC adapter may be connected to the mobile device for the purpose of reducing the discharge of the battery or for the purpose of charging the battery in a case where the installed battery is a secondary battery. In the case where the installed battery is a secondary battery, it is preferable to allow the power supply of the AC adapter to charge the secondary battery while supplying power to respective circuits in the mobile device.
FIG. 3 shows an exemplary circuit diagram of a conventional power switching circuit (see, for example, Japanese Registered Patent Publication No. 3195052). The power switching circuit 100 shown in FIG. 3 includes a main power supply 101, a backup power supply 102, a switching control circuit 105, a comparator 106, a reference voltage source 107, PMOS transistors P101, P102, inverters G101, G102, and resistors R101-R103. The power switching circuit 100 includes an output terminal 103, a main power supply terminal Vcc, and a backup power supply terminal VBAT. It is to be noted that Vcc also indicates a main power supply voltage.
The main power supply 101 is connected to the output terminal 103 via the PMOS transistor P101, and the backup power supply 102 is connected to the output terminal 103 via the PMOS transistor P102.
The voltage Vcc of the main power supply 101 is divided by the resistors R101 and R102 that are connected in series. The divided voltage is input to a non-inverting input terminal of the comparator 106. The reference voltage source 107 is connected to an inverting input terminal of the comparator 106. An output terminal of the comparator 106 is connected to an input terminal of the inverter G101, and an output terminal of the inverter G101 is connected to an input terminal of the inverter G102. Furthermore, the output terminal of the inverter G101 is connected to a gate of the PMOS transistor P101, and an output terminal of the inverter G102 is connected to a gate of the PMOS transistor P102.
In a case where the voltage Vcc of the main power supply 101 is sufficiently high, the voltage at the intersecting point between the resistor R101 and the resistor R102 is equal to or greater than the voltage output from the reference voltage source 107. Thereby, the output terminal of the comparator 106 is a high level. In this case, the output terminal of the inverter G101 is a low level, and the PMOS transistor P101 is on. Thereby, the main power supply 101 is connected to the output terminal 103. Meanwhile, the output terminal of the inverter G102 is a high level, and the PMOS transistor P102 is off. Thereby, the backup power supply 102 is not connected to the output terminal 103. Accordingly, only the electric power of the main power supply 101 is supplied to the output terminal 103.
In a case where the voltage Vcc of the main power supply 101 decreases to a level causing the voltage at the intersecting point between the resistor R101 and the resistor R102 to become less than the voltage output from the reference voltage source 107, the signal level of the output terminal of the comparator 106 becomes inverted and becomes a low level. In this case, the output terminal of the inverter G101 becomes a high level, and the PMOS transistor P101 is switched off. Thereby, the main power supply 101 and the output terminal 103 become disconnected. Meanwhile, the output terminal of the inverter G102 becomes a low level, and the PMOS transistor P102 is switched on. Thereby, the backup power supply 102 becomes connected to the output terminal 103. As a result, only the power from the backup power supply 102 is supplied to the output terminal 103.
FIG. 4 is an exemplary circuit diagram showing another power switching circuit (see, for example, Japanese Laid-Open Patent Application No. 2003-339125). The power switching circuit 110 shown in FIG. 4 includes a main power supply part 111, a backup power supply part 112, a system circuit 114 serving as a load, a reverse flow preventing diode D111, and a low voltage detecting circuit 113. The main power supply part 111 includes a main battery 121 and a first power supply circuit 122. The backup power supply part 112 includes a primary battery 131 and a second power supply circuit 132. The first power supply circuit 122 and the second power supply circuit 132 are configured to output substantially the same level of voltage.
In a case where the voltage of the main battery 121 is high, the operation of the second power supply circuit 132 of the backup power supply part 112 is shut down (stopped) by signals output from the low voltage detecting circuit 113. The second power supply circuit 132 operates only when the voltage of the main battery 121 becomes lower than a predetermined value. Therefore, even in a case where the system voltage V becomes temporarily low, no power is supplied to the system circuit 114 from the backup power supply part 112. Thereby, the primary battery 131 of the backup power supply part 112 can be prevented from being discharged.
In the power switching circuit 100 shown in FIG. 3, the voltage Vcc of the main power supply 101, which is output from the output terminal 103, is detected directly. Therefore, in a case where the voltage divided at the resistors R101 and R102 is near the output voltage of the reference voltage source 107, slight changes in the voltage Vcc of the main power supply 101 due to subtle changes of load cause the main power supply 101 and the backup power supply 102 to be switched frequently, that is, the voltage output from the output terminal 103 is frequently switched between main power supply voltage Vcc and backup power supply voltage VBAT. As a result, in a case where the output terminal 103 is connected to a load circuit, the load circuit is adversely affected by the frequent switching of voltage. In addition, since the power switching circuit 100 shown in FIG. 3 is configured to switch to the backup power supply 102 when the voltage Vcc of the main power supply 101 decreases to some level, the power switching circuit 100 cannot be used for applications where changes in the voltage of the output terminal 103 are required to be minimal.
The power switching circuit 110 shown in FIG. 4 includes the first power supply circuit 122 provided in the main power supply part 111 and the second power supply circuit 132 provided in the backup power supply part 112 in correspondence with the first power supply circuit 110. Furthermore, low voltage detection is performed at the main battery 121. Therefore, with this configuration, changes in the voltage of the system voltage V can be controlled to a low level even in a case where the main power supply part 111 and the backup power supply part 112 are switched back and forth. However, in a case where the second power supply circuit part 132 of the backup power supply part 112 is activated when the voltage of the main battery 121 becomes low, there is no countermeasure for preventing the current from flowing in from the backup power supply part 112 to the output terminal of the main power supply part 111. Therefore, the power switching circuit 110 is unable to prevent reverse flow of current from the backup power supply part 112 to the main power supply part 111. In addition, even after the second power supply circuit 132 of the backup power supply circuit part 112 is activated due to a drop in the voltage of the main battery 121, some amount of time is required for the second power supply circuit 132 to output a rated output voltage. Accordingly, the voltage of the system power supply V temporarily drops to a considerably low level, to thereby adversely affect the system circuit 114.